A Novel Dynamic Threshold Operation Using the Electrically Induced Junction MOSFET in the Deep sub-micrometer CMOS Regime

With CMOS scaling into the Sub-100nm regime, the supply and the threshold voltages need to be scaled proportionately. This necessitates addressing of low power CMOS device design issues. The idea of a Dynamic Threshold MOSFET (DTMOS), without the associated substrate loading effects, is a key to addressing the problems associated with device scaling for low power CMOS. This work focuses on the device optimisation for such low power ULSI circuits using a novel Electrically induced junction (EJ)-MOSFET as a DTMOS. Such an implementation can be used without the additional substrate loading effects and the supply voltage limitations, commonly associated with conventional DTMOS operation. Our detailed dc as well as transient simulations bring out the advantages of this novel structure.